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Anurag
Anurag
Project Associate
Contact Information
125, Phase-4, Mohali, India
Tel: +919781958768
Email ID: anuragece09[at]gmail.com
Educational Background
2011-2013: M. Tech in VLSI Design (Centre for Development of Advanced Computing (C-DAC), Mohali, India )
2005-2009: B.E in Electronics & Communication (Birla Institute of Applied Sciences, Bhimtal, Nainital, India)
Positions Held
Aug 2013 - Dec 2013: Guest Faculty at University Institute of Engineering & Technology, Punjab University, Chandigarh
Jan 2010 - Jan 2011: VHDL Training Coordinator at Cybrain Software Solutions Phase-7, Mohali, India
Research Interest
Low Power VLSI Design
RTL and FPGA Design
Conferences and Workshops
Attended a short Term Course on ”Embedded System and HDL (ESHDL-13)” held on 20th to 24th may 2013 in NIT, Hamirpur, H.P.
Selected Publications
Anurag, Gurmohan Singh, V. Sulochana, “Low Power Dual Edge - Triggered Static D Flip-Flop”, International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, pp-23-29, June 2013.