Gurmohan Singh

Gurmohan Singh

Senior Engineer

Contact Information

Tel: +919417483045
Email ID: gurmohan[at]

Educational Background

  • Pursuing PhD (National Institute of Technology, Jalandhar, India)
  • 2003-2005: M.Tech in Microelectronics, Panjab University, Chandigarh, India
  • 1997-2001:B.Tech in Electronics & Communication Engg., Giani Zail Singh College of Engg. & Tech. Bathinda, India

Positions Held

  • Jan. 2009- July 2012: Worked as Junior Telecom Officer in Bharat Sanchar Nigam Limited (BSNL) at Telecom Project Division, Chandigarh.
  • Nov. 2005-Jan 2009: Worked as Design Engineer (VLSI R&D) in Centre for Development of Advanced Computing, Mohali.

Research Interest

  • Modeling of emerging nanoscale CMOS devices, Computational Nanoscience, Molecular electronics, MEMS/NEMS Sensors, Band Gap Engineering in heterostructures.
  • System-on-Chip Design issues & solutions, High-Level Synthesis (HLS) Techniques, Design for Manufacturability (DFM), VLSI Signal Interconnect issues & solutions in nanoscale CMOS technologies.

Academic Awards and Other Achievements

  • Secured 2nd position in JTO Phase-II training in Transmission Technologies during 5/7/2010 to 13/8/2010 at Bharat Ratna Bhim Rao Ambedkar Institute of Telecomm Training (BRBRAITT), Jabalpur , A Premier National Level Telecommunication Training Center of BSNL.
  • Received Certificate of Merit for securing 2nd position in essay writing competition held at C-DAC Mohali During Vigilence Awareness Week 2013.
  • Qualified Graduate Aptitude Test in Engineering (GATE) in 2014 & 2003 respectively.

Professional Memberships

  • Life Member Indian Microelectronics Society (IMS)

Selected Publications

  1. Analysis of Low Power CMOS Current Comparison Domino Logic circuits in ultra deep submicron technologies, International Journal of Computer Applications (0975 – 8887), Volume 88 – No.7, February 2014.
  2. High Performance Low Power Dual Edge – Triggered Static D Flip-Flop, 4th IEEE Conference on Computing, Communication & Networking Technologies (ICCCNT-2013), 4th-6th July 2013 at Vivekanandha College of Engineering for Women, Tiruchengode.
  3. Low Power Dual Edge – Triggered Static D Flip-Flop, International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, pp-23-29, June 2013.
  4. A Unified Codec Scheme for reduction of Area and Crosstalk in RC and RLC Modeled Interconnects using both Bus Encoding and Shielding Insertion Technique, International Journal of Electrical and Computer Engineering (IJECE), Vol. 3, No. 4, August 2013, pp. 524~532 ISSN: 2088-8708. A Low Power 32 Bit CMOS ROM Using a Novel ATD Circuit, International Journal of Electrical and Computer Engineering (IJECE),Vol. 3, No. 4, pp. 509~515, August 2013.
  5. Development of FPGA- based Dual Axis Solar Tracking System, American Transactions on Engineering & Applied Sciences, Volume 2, No. 4, ISSN 2229-1652, eISSN 2229-1660.
  6. Novel High Gain Low Noise CMOS Instrumentation Amplifier for Biomedical Application, IEEE sponsored International Conference on Machine Intelligence Research and Advancement (ICMIRA)-2013 at Mata Vaishno Devi University Dec 2013.
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